Dynamic logic circuit designs are utilized in integrated circuit design to realize increases in digital circuit operating frequencies as compared to static logic circuit designs. Domino logic circuits represent a class of dynamic logic circuits. A single domino logic gate circuit design typically includes an NMOS pull-down network, two or more clock-controlled transistors, and a static logic gate which is used as a buffer between dynamic nodes within successive domino logic gate circuits. The domino logic gate circuit pre-charges the dynamic node of the static gate to a logic high state during a first phase of a clock signal used to clock the clock-controlled transistors, typically when the clock signal is low. The domino logic gate circuit subsequently evaluates the logic gate in a second phase of the clock signal. In particular, the dynamic node either discharges or retains its pre-charged state depending upon values of input signals applied to the logic gate.
A dynamic-to-static converter circuit is used within integrated circuits to convert dynamic logic circuit signals based upon a clock signal to static logic circuit signals for use within the integrated circuit. The dynamic-to-static converter circuit includes a dynamic logic gate circuit and a latch circuit in which an output signal from the latch circuit represents the converted static logic signal. Both the dynamic logic gate circuit and the latch circuit are controlled by a common clock signal such that the latch captures a current value of the dynamic logic gate output at a proper point of time within the dynamic logic timing cycle.
Unfortunately, the use of a common clock signal, as is typically utilized within stages of dynamic logic circuits, may permit the output signal generated by the latch circuit to briefly propagate an erroneous representation of the dynamic logic gate output under certain conditions. When the common clock signal is used to drive evaluation of a pre-charged dynamic logic gate and at the same time enable the latch circuit to capture the value of the signal value from the dynamic logic gate, a signal input to the latch circuit may observe and propagate an erroneous logic value for the dynamic logic gate circuit during a brief period of time while the logic signal is still under evaluation by the dynamic logic circuit. The erroneous logic value may appear to subsequent logic circuits receiving an output signal from the dynamic-to-static converter circuit as a signal glitch. This signal glitch can cause a functional failure if it propagates out of the latch and is sampled by a sequential element. In addition, the glitch may result in wasted power consumption due to unnecessary latch activity incident to the glitch. Hence, this signal glitch can present design issues for the subsequent logic circuits that make use of the static logic signal without the aid of a clock signal.